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====== DAC ======

The LCD breakout has 6 bit x RGB output, which we can turn into a 6-bit DAC -> RGB analog 0.7Vpp into 75 ohms
use 278 & 556 ohm resistors for the R2R ladder, this will give you ~0.7v signal when plugged into a 75 ohm termination such as a monitor. 

====== VSync ======

We want to get the Vsync to about 60hz

By default, the 'internal' LCD sync rate is 117 Hz
<code>
chumby-:/ # cat /proc/driver/chumbyfwfb/fb_stats
PXP frequency:          59 Hz
LCDIF frequency:        117 Hz
VSYNC Edge IRQs:        49077
Cur Frame Done IRQs:    49224
Missed PXP firings:     5
</code>

This is set by the  HW_CLKCTRL_PIX register

<code>
chumby-:/ # regutil -r HW_CLKCTRL_PIX
Value at 0x80040060: 0x0000001d
</code>

Lets divide the frequency by 2 which means multiplying the divider by two

<code>
chumby-:/ # regutil -w HW_CLKCTRL_PIX=0x38
Setting 0x80040060: 0x0000000e -> 0x00000038 ok
</code>

<code>
chumby-:/ # cat /proc/driver/chumbyfwfb/fb_stats
PXP frequency:          32 Hz
LCDIF frequency:        62 Hz
VSYNC Edge IRQs:        69919
Cur Frame Done IRQs:    70118
Missed PXP firings:     5
</code>

Actually, to get the closest to 60 Hz. I went with HW_CLKCTRL_PIX=0x37 (so says the tek 'scope)

How the Hsync is 17.08 KHz (we want 2x that 31.46 KHz)


THIS IS ALL WRONG. START OVER!

====== Horizontal Sync HW_LCDIF_VDCTRL2======

For the LCD, this is by default = 0x45000190

Per horizontal line: 640 pixels
Front porch: 16 pixels
Sync pulse width: 96 pixels
Back porch: 48 pixels

SO!

HW_LCDIF_VDCTRL2 = (96) << 24 | (640 + 16 + 48) = 0x600002C0

====== Vsync HW_LCDIF_VDCTRL1 ======

For the LCD, this is by default = 0x0000011a (dec. 282)

Per vertical line: 480 horizontal lines
Front porch: 11 horizontal lines
Sync pulse: 2 horizontal lines
back porch: 31 horizontal lines

so HW_LCDIF_VDCTRL1 = 542 (0x21e)

====== HW_LCDIF_VDCTRL0 ======

VSYNC_OEB = 0 (generate vsync)
ENABLE_PRESENT = 0 (no enable necessary)
0x0

VSYNC_POL = 0 (negative sync!)
HSYNC_POL = 0 (negative sync!)
DOTCLK_POL = D/C
ENABLE_POL = D/C
0x0

VSYNC_PERIOD_UNIT = 1 (count in lines)
VSYNC_PULSE_WIDTH_UNIT = 1 (count in lines)
0x3

HALF_LINE = 0 
HALF_LINE_MODE = 1 (no half line for vga, right?)
0x4

VSYNC_PULSE_WIDTH = 2 
0x2

-> 0x00340002

====== HW_LCDIF_TRANSFER_COUNT ======
By default, (32x0x240 LCD) =  0x00f00140

For 640x480 VGA it should be = 0x01E00280

====== HW_CLKCTRL_PIX ======

CLKGATE = 0
DIV = 0x11 

===== Results? =====

HSync = 31.4Khz (should be 31.46)
Vsync = 58 Hz (should be 60.04)

Vsync negative pulse = 63.7 uS (should be 63.57) (it is low from the negative edge of one HSync to another negative Hsync edge)
Hsync negative pulse = 4.34 uS (should be 3.81)
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