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--- chumbyhackerboard:vga [2010/09/21 04:45]
ladyada
+++ chumbyhackerboard:vga [2010/09/21 05:38]
ladyada
@@ Line 4: / Line 4: @@
 use 278 & 556 ohm resistors for the R2R ladder, this will give you ~0.7v signal when plugged into a 75 ohm termination such as a monitor.
-====== VSync ======
-We want to get the Vsync to about 60hz
-By default, the 'internal' LCD sync rate is 117 Hz
-<code>
-chumby-:/ # cat /proc/driver/chumbyfwfb/fb_stats
-PXP frequency:          59 Hz
-LCDIF frequency:        117 Hz
-VSYNC Edge IRQs:        49077
-Cur Frame Done IRQs:    49224
-Missed PXP firings:     5
-</code>
-This is set by the  HW_CLKCTRL_PIX register
-<code>
-chumby-:/ # regutil -r HW_CLKCTRL_PIX
-Value at 0x80040060: 0x0000001d
-</code>
-Lets divide the frequency by 2 which means multiplying the divider by two
-<code>
-chumby-:/ # regutil -w HW_CLKCTRL_PIX=0x38
-Setting 0x80040060: 0x0000000e -> 0x00000038 ok
-</code>
-<code>
-chumby-:/ # cat /proc/driver/chumbyfwfb/fb_stats
-PXP frequency:          32 Hz
-LCDIF frequency:        62 Hz
-VSYNC Edge IRQs:        69919
-Cur Frame Done IRQs:    70118
-Missed PXP firings:     5
-</code>
-Actually, to get the closest to 60 Hz. I went with HW_CLKCTRL_PIX=0x37 (so says the tek 'scope)
-How the Hsync is 17.08 KHz (we want 2x that 31.46 KHz)
-THIS IS ALL WRONG. START OVER!
 ====== Horizontal Sync HW_LCDIF_VDCTRL2======
@@ Line 52: / Line 10: @@
 For the LCD, this is by default = 0x45000190
-Per horizontal line: 640 pixels
+We want...
-Front porch: 16 pixels
-Sync pulse width: 96 pixels
+  * Per horizontal line: 640 pixels
-Back porch: 48 pixels
+  * Front porch: 16 pixels
+  * Sync pulse width: 96 pixels
+  * Back porch: 48 pixels
 SO!
-HW_LCDIF_VDCTRL2 = (96) << 24 | (640 + 16 + 48) = 0x600002C0
+HW_LCDIF_VDCTRL2 = (96) << 24 | (640 + 16 + 96+ 48) = 0x60000320
 ====== Vsync HW_LCDIF_VDCTRL1 ======
@@ Line 65: / Line 25: @@
 For the LCD, this is by default = 0x0000011a (dec. 282)
-Per vertical line: 480 horizontal lines
+We want...
-Front porch: 11 horizontal lines
-Sync pulse: 2 horizontal lines
-back porch: 31 horizontal lines
-so HW_LCDIF_VDCTRL1 = 542 (0x21e)
+  * Per vertical line: 480 horizontal lines
+  * Front porch: 11 horizontal lines
+  * Sync pulse: 2 horizontal lines
+  * back porch: 31 horizontal lines
+so HW_LCDIF_VDCTRL1 = 524 (0x20C)
 ====== HW_LCDIF_VDCTRL0 ======
+<file>
 VSYNC_OEB = 0 (generate vsync)
 ENABLE_PRESENT = 0 (no enable necessary)
@@ Line 94: / Line 57: @@
 VSYNC_PULSE_WIDTH = 2
 x2
+</file>
 -> 0x00340002
+====== HW_LCDIF_VDCTRL3 ======
+by default = 0x004b0027
+  * MUX_SYNC_SIGNALS = 0
+  * VSYNC_ONLY = 1 (?)
+  * HORIZONTAL_WAIT_CNT = 48 (h back porch) + 96 (sync pulse) = 0xDE and then
+  * VERTICAL_WAIT_CNT = 31 (v back porch) + 2 (sync pulse) = 0x21
+-> 0x00DE0021
 ====== HW_LCDIF_TRANSFER_COUNT ======
@@ Line 104: / Line 78: @@
 ====== HW_CLKCTRL_PIX ======
+So the main clock is 454 right?
+To get a pixel clock of 25.175 MHz, 454 MHz / 18 -> DIV = 0x12
 CLKGATE = 0
-DIV = 0x11
+DIV = 0x12 -> CLK of 21 Mhz
+Hmm, guess our chip isnt running at 454? Or is it our scope? Try 0x0F for 25MHz  which matches with eveything else. Which means we're running at 375MHz?
+===== Results? =====
+PIXCLK = 0x0F
+HSync = 31.3Khz (should be 31.46)
-To get HSync of 31.4Khz & Vsync of 58 Hz
+Vsync = 59.75 Hz (should be 60.04)
+Vsync negative pulse = 63.9 uS (should be 63.57) (it is low from the negative edge of one HSync to another negative Hsync edge)
+Hsync negative pulse = 3.83 uS (should be 3.81)
+HSync Back porch = 5 uS (should be 1.9?), Hsync front porch = ~14.2uS (should be 0.65?)

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